Reference is now made to FIG. 1 showing the general configuration of a conventional lateral bipolar junction transistor (BJT) 10 device. A silicon-on-insulator substrate 12 supports the transistor. The substrate 12 includes a substrate layer 14, a buried oxide (BOX) layer 16 and a semiconductor layer 18. An active region 20 for the transistor device is delimited by a peripherally surrounding shallow trench isolation 22 which penetrates through the layer 18. Within the active region 20, the layer 18 is divided into a base region 30 which has been doped with a first conductivity type dopant, an emitter region 32 (adjacent the base region 30 on one side) which has been doped with a second conductivity type dopant, and a collector region 34 (adjacent the base region 30 on an opposite side from the emitter region 32) which has also been doped with the second conductivity type dopant. Where the BJT 10 device is of the npn-type, the first conductivity type dopant is p-type and the second conductivity type is n-type. Conversely, where the BJT device is of the pnp-type, the first conductivity type dopant is n-type and the second conductivity type is p-type. An extrinsic base region 36 is provided above the base region 30. This extrinsic base region 36 typically comprises polysilicon material and is heavily doped with the same conductivity type dopant as the base region 30 provided in the layer 18. Sidewall spacers 38 made of an insulating material such as silicon nitride (SiN) are provided on the sides of the extrinsic base region 36 and serve to protect against shorting of the emitter (E) or collector (C) to the base (B).
There are a few concerns with the BJT 10 device as shown in FIG. 1. One concern is that it is difficult to heavily dope the polysilicon material used for the extrinsic base region 36. A high dopant concentration in the extrinsic base region 36 is difficult to achieve without risking adversely impacting the dopant in the base region 30. Another concern is that a too high interfacial density of state (Dit) condition exists at the bottom of the silicon nitride sidewall spacers 38 on the layer 18 which overlap the interface between the emitter/collector regions and the base region 30.
A need accordingly exists in the art for an improved configuration of a lateral BJT device implemented on an SOI substrate.